Computer systems incorporating the Industry Standard Architecture (ISA) compliant interrupt scheme are well-known in the prior art. FIG. 1 is a block diagram of one such computer system 10. The computer system 10 is shown to include a micro-processor 50, two peripheral devices 20 and 40, a set of interrupt request lines IRQ0-15, and an interrupt controller 70.
The peripheral device 40 is shown connected to interrupt signal lines IRQ0-15. An exemplary embodiment of the peripheral device 40 is available from Cirrus Logic Inc. as part number CL-PD6729. The peripheral device 40 generates an interrupt request signal on one of the interrupt request lines IRQ0-15 when it requires attention from the micro-processor 50. Such attention is usually required when there is some activity associated with an input/output (I/O) device attached to the peripheral device 40. For example, if a fax modem (not shown in the diagram) is attached to the peripheral device 40, and if the fax modem needs to communicate with the microprocessor 50, the peripheral device 40 generates an interrupt request signal.
The peripheral device 20 operates similar to peripheral device 40, and is also shown connected to interrupt request signal lines IRQ0-15. Both the peripheral devices 20, 40 may thus share the interrupt request signal lines IRQ0-15. The peripheral devices 20, 40 may each optionally be coupled to only a subset of the interrupt request lines IRQ0-15.
The interrupt controller 70 continuously monitors each of the interrupt request lines IRQ0-15 for an interrupt request signal. On receiving an interrupt request signal, the interrupt controller 70 typically sends a signal to the microprocessor 50 over a signal line 75 indicating the presence of an interrupt to be processed on the peripheral device. The processor 50 usually polls the peripheral devices 20,40 and processes the interrupt on the peripheral device.
It is further known in the prior art that different types of signals such as a pulse signal or a level signal can be used for the interrupt request signals. FIG. 2A shows a pulse signal of the prior art. In the case of a pulse signal, the interrupt request signal lines IRQ0-15 are normally in a high impedance state (shown during clock cycles 101-102). To generate an interrupt signal, the peripheral device 40 first drives the interrupt request line to an active low (shown during clock cycle 103), and then to an active high (shown during clock cycle 104). The signal levels can span multiple clock cycles. The peripheral device then drives the interrupt request signal line back to the high-impedance state.
FIG. 2B illustrates a level signal that can be used to signal an interrupt request signal. Here, an active high (shown during clock cycle 151 ) usually signals an interrupt request signal. The interrupt signal lines IRQ0-15 otherwise are driven to a low signal level shown during clock cycle 150, 152, and 153. On sensing the interrupt request, the interrupt controller 70 sends a signal to the processor 50 to indicate the presence of an interrupt.
Recently, many computer system manufacturers have embraced another standard--peripheral component interconnect (PCI). This has lead to incorporation of the PCI interrupt scheme into many computer systems. FIG. 3 illustrates a computer system 300 incorporating the PCI interrupt scheme. Significantly, the computer system 300 includes only four interrupt request lines--INTA, INTB, INTC, and INTD. The computer system 300 is also shown with two peripheral devices 320, 340, an interrupt controller 360, and a processor 370.
The peripheral devices 320, 340 send an interrupt request signal over the interrupt request lines INTA-D to request the attention of the processor 350. The interrupt controller 370 sends a signal indicating the presence of the interrupt on the peripheral devices, and the processor 370 processes the interrupt on the peripheral devices 320, 340. For a more information on the PCI interrupt structure, the reader is referred to "PCI Local Bus Specification 2.0/2.1" which specification is incorporated herein by reference.
While the number of PCI compliant computer systems has grown recently, the ISA compliant systems continue to constitute a significant portion of the computer system market. A large portion of the software and hardware continues to be used that operates around the ISA interrupt scheme.
It has therefore become advantageous to design peripheral devices that can operate in conjunction with both the PCI interrupt scheme and the ISA interrupt scheme. Such a peripheral device can be conveniently used in either an ISA compliant system or a PCI compliant system. Due to the economies of scale associated with manufacturing a single device for both types of systems, significant cost savings can be realized. The availability of a single device to serve both type of systems avoids needless confusion that otherwise usually results in the users.
One problem that has been encountered with the design of a peripheral device that can operate with both the interrupt schemes is the differing number of pins required to support the interrupt structures of the two schemes. While the PCI interrupt structure uses only four interrupt request lines, the ISA interrupt structure could potentially use sixteen signal lines. Therefore, an ISA compliant peripheral device would require up to sixteen pins, while the PCI compliant peripheral device would require up to only four pins.
One prior solution has implemented a peripheral device with fourteen pins--ten to interface with an ISA compliant system, and the other four to interface with a PCI compliant system. This prior solution has the disadvantage that a substantial number of pins in the peripheral device remain unused when the dual-compliant peripheral device is used in a PCI compliant system. An increase in number of pins usually results in an increased manufacturing costs. The problem may be compounded if the increase in number of pins forces the integrated circuit to be packaged in a package with a higher number of pins, for example from 208 to 256 pins.
It is therefore desirable to design a peripheral device that will not require these additional pins when the peripheral device is used in the PCI systems. It is further required that this peripheral device be operable in ISA systems also.